Reset device

  • Inventors: ABE SHUHEI
  • Assignees: Shuhei Abe
  • Publication Date: May 08, 2008
  • Publication Number: US-2008106309-A1

Abstract

A disclosed reset device for outputting a reset signal based on a magnitude of an input power supply voltage includes: a power supply voltage monitoring unit including a comparator to which a detection voltage detected based on the magnitude of the power supply voltage and a reference voltage to be used as an inversion reference for the reset signal are input, the comparator comparing the detection voltage with the reference voltage and outputting an output voltage in accordance with a result of the comparison; and a reset signal outputting unit including a CMOS inverter to which the output voltage output from the power supply voltage monitoring unit is input, the unit outputting the reset signal. An impedance unit is disposed between a P-channel MOS transistor constituting the inverter and a power supply voltage line and/or between an N-channel MOS transistor constituting the inverter and a ground line.

Claims

1 . A reset device for outputting a reset signal based on a magnitude of an input power supply voltage, comprising: a power supply voltage monitoring unit including a comparator to which a detection voltage detected based on the magnitude of the power supply voltage and a reference voltage to be used as an inversion reference for the reset signal are input, the comparator comparing the detection voltage with the reference voltage and outputting an output voltage in accordance with a result of the comparison; and a reset signal outputting unit including a CMOS inverter to which the output voltage output from the power supply voltage monitoring unit is input, the reset signal outputting unit outputting the reset signal, wherein an impedance unit is disposed between a P-channel MOS transistor constituting the inverter and a power supply voltage line and/or between an N-channel MOS transistor constituting the inverter and a ground line. 2 . The reset device according to claim 1 , wherein the impedance unit is a resistance element having a resistance value within a range from not less than 100 kΩ to not more than 3 MΩ. 3 . The reset device according to claim 1 , wherein the inverter is disposed in plural stages. 4 . The reset device according to claim 2 , wherein the inverter is disposed in plural stages. 5 . The reset device according to claim 3 , wherein in the reset signal outputting unit, the inverter including the impedance unit disposed between the N-channel MOS transistor and the ground line and the inverter including the impedance unit disposed between the P-channel MOS transistor and the power supply voltage line are disposed as continuous stages. 6 . The reset device according to claim 4 , wherein in the reset signal outputting unit, the inverter including the impedance unit disposed between the N-channel MOS transistor and the ground line and the inverter including the impedance unit disposed between the P-channel MOS transistor and the power supply voltage line are disposed as continuous stages.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to a reset device and more particularly to a reset device outputting a reset signal in accordance with the magnitude of an input power supply voltage. [0003] 2. Description of the Related Art [0004] Conventionally, there have been known circuits for generating a reset signal in which a reset signal is generated based on a change of power supply voltage and an initial setting of a system is performed so as to prevent malfunction of a device resulting from an indefinite state of an output logic upon power-on operation of a system on which a CMOS logical circuit such as a flip-flop is mounted (refer to Patent Document 1, for example). [0005] FIG. 1 is a diagram showing a conventional circuit for generating a reset signal. The reset signal generating circuit shown in FIG. 1 includes N-channel MOS transistors 110 and 120 , a resistor 130 , an inverter 150 , an OR operator 180 , and an RS flip-flop 190 . The inverter 150 is constructed as a CMOS inverter and includes a P-channel MOS transistor 160 and an N-channel MOS transistor 170 . [0006] In FIG. 1 , when a power supply voltage VDD is applied from an input terminal, a voltage V N1 of a node N 1 is expressed as VDD-2V TH divided using the resistor 130 , where threshold voltages of the N-channel MOS transistors 110 and 120 are V TH . On the other hand, thresholds of the P-channel MOS transistor 160 and the N-channel MOS transistor 170 correspond to those of N-channel MOS transistors 110 and 120 , respectively, so that a threshold voltage V TH1 of the inverter 150 is VDD/2. When the voltage V N1 of the node N 1 is larger than the threshold voltage V TH1 of the inverter 150 , the N-channel MOS transistor 170 conducts and outputs an L-level reset signal. By contrast, when the voltage V N1 of the node N 1 is smaller than the threshold voltage V TH1 of the inverter 150 , the P-channel MOS transistor 160 conducts and outputs an H-level reset signal. [0007] FIGS. 2A and 2B are waveform charts illustrating operation of a reset signal generating circuit corresponding to the conventional technique shown in FIG. 1 . In FIG. 2A , L A indicates a temporal change of the power supply voltage VDD and L B indicates a temporal change of the node voltage V N1 . Further, V TH1 indicates the threshold voltage of the inverter 150 . In this case, the threshold voltage V TH1 of the inverter 150 changes at a half of the temporal change L A of the power supply voltage VDD and when the node voltage V N1 does not exceed the threshold voltage V TH1 of the inverter 150 , a reset signal R is output at the H level. Then, when the node voltage V N1 exceeds the threshold voltage V TH1 of the inverter 150 , the reset signal R is output at an L level. Further, when the reset signal R is output at the H level, the RS flip-flop 190 is reset and when the reset signal R is output at the L level, logic is maintained. [0008] By constructing in this manner, the reset signal R is output at the H level until the power supply voltage VDD becomes twice the threshold voltage V TH of the N-channel MOS transistors 110 and 120 . [0009] Patent Document 1: Japanese Laid-Open Patent Application No. 9-181586 [0010] However, in the structure disclosed in above-mentioned Patent Document 1, the inverter 150 may be subject to malfunction when the power supply voltage is rapidly changed. [0011] FIGS. 3A , 3 B, 3 C, and 3 D are diagrams illustrating problems of a CMOS inverter 150 a according to the conventional technique. FIG. 3A shows a configuration of the conventional CMOS inverter 150 a . In FIG. 3A , the CMOS inverter 150 a includes a P-channel MOS transistor 160 a and an N-channel MOS transistor 170 a . An input VIN is constructed as a common gate an output Vout is constructed as a common drain. A source of the N-channel MOS transistor 170 a is connected to a ground line and a source of the P-channel MOS transistor 160 a is connected to a power supply voltage VDD line. The CMOS inverter 150 a is constructed such that when a voltage at the H level is input to the VIN, the N-channel MOS transistor 170 a conducts and outputs at the L level, and when a voltage at the L level is input to the VIN, the P-channel MOS transistor 160 a conducts and outputs at the H level. [0012] The following describes a case where the power supply voltage VDD shown in FIG. 3B is input to the CMOS inverter 150 a constructed in this manner. FIG. 3B shows a case where the power supply voltage VDD is input at a substantially constant voltage and a rapid voltage change is generated due to a sudden voltage change at the power supply voltage. In this case, as shown in FIG. 3C , the input voltage VIN of the CMOS inverter 150 a is raised due to capacity coupling following the rapid change of the power supply voltage. When the value exceeds a threshold V th =VDD/2 of the CMOS inverter 150 a , as shown in FIG. 3D , the Vout required to be maintained at the H level is changed to be at the L level under the influence of the VIN exceeding the threshold. In this manner, the configuration shown in FIG. 3A poses problems in that the CMOS inverter 150 a may be subject to malfunction due to the rapid change of the power supply voltage. SUMMARY OF THE INVENTION [0013] It is a general object of the present invention to provide an improved and useful reset device in which the above-mentioned problems are eliminated. [0014] A more specific object of the present invention is to provide a reset device that can output a reset signal in a stable manner without causing malfunction of a CMOS inverter even when a power supply voltage is rapidly changed. [0015] According to the present invention, there is provided a reset device for outputting a reset signal based on a magnitude of an input power supply voltage, comprising: a power supply voltage monitoring unit including a comparator to which a detection voltage detected based on the magnitude of the power supply voltage and a reference voltage to be used as an inversion reference for the reset signal are input, the comparator comparing the detection voltage with the reference voltage and outputting an output voltage in accordance with a result of the comparison; and a reset signal outputting unit including a CMOS inverter to which the output voltage output from the power supply voltage monitoring unit is input, the reset signal outputting unit outputting the reset signal, wherein an impedance unit is disposed between a P-channel MOS transistor constituting the inverter and a power supply voltage line and/or between an N-channel MOS transistor constituting the inverter and a ground line. In accordance with this, it is possible to adjust a switching voltage for switching output levels for the reset signal of the CMOS inverter and to set the switching voltage such that the output levels remain unchanged even when the power supply voltage is rapidly changed. [0016] According to another aspect of the present invention, in the reset device, the impedance unit may be a resistance element having a resistance value within a range from not less than 100 kΩ to not more than 3 MΩ. In accordance with this, it is possible to set the switching voltage in the CMOS inverter to be a value within an appropriate range. [0017] According to another aspect of the present invention, in the reset device, the inverter may be disposed in plural stages. In accordance with this, it is possible to set the switching voltage in the CMOS inverter in accordance with any combination. [0018] According to another aspect of the present invention, in the reset signal outputting unit of the reset device, the inverter including the impedance unit disposed between the N-channel MOS transistor and the ground line and the inverter including the impedance unit disposed between the P-channel MOS transistor and the power supply voltage line may be disposed as continuous stages. In accordance with this, it is possible to set the switching voltage in the CMOS inverter in plural stages when the switching voltage is set to be large. [0019] According to the present invention, the switching voltage in the CMOS inverter of the reset device is readily adjusted using the impedance unit. Thus, it is possible to provide a reset device capable of outputting a reset signal in a stable manner without being influenced by a change of the power supply voltage. [0020] Other objects, features and advantage of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0021] FIG. 1 is a circuit diagram showing a configuration of a conventional circuit for generating a reset signal; [0022] FIG. 2A is a waveform chart illustrating operation of a reset signal generating circuit corresponding to a conventional technique shown in FIG. 1 ; [0023] FIG. 2B is a waveform chart illustrating operation of a reset signal generating circuit corresponding to a conventional technique shown in FIG. 1 ; [0024] FIG. 3A is a circuit diagram showing a configuration of a conventional CMOS inverter; [0025] FIG. 3B is a waveform chart illustrating problems of a conventional CMOS inverter; [0026] FIG. 3C is a waveform chart illustrating problems of a conventional CMOS inverter; [0027] FIG. 3D is a waveform chart illustrating problems of a conventional CMOS inverter; [0028] FIG. 4 is a circuit diagram showing an embodiment of a reset device to which the present invention is applied; [0029] FIG. 5A a circuit diagram showing a configuration of a CMOS inverter in an enlarged manner; [0030] FIG. 5B is a waveform chart illustrating a power supply voltage VDD of a CMOS inverter; [0031] FIG. 5C is a waveform chart illustrating an input VIN of a CMOS inverter; [0032] FIG. 5D is a waveform chart illustrating an output Vout of a CMOS inverter; [0033] FIG. 6 is a diagram showing a relationship between a resistance value and a switching voltage when a resistor is inserted between a source of a P-channel MOS transistor and a power supply voltage line; [0034] FIG. 7 is a diagram showing a relationship between a resistance value and a switching voltage when a resistor is inserted between a source of an N-channel MOS transistor and a power supply voltage line; [0035] FIG. 8 is a circuit diagram showing a configuration of a CMOS inverter as a variation in a reset device shown in FIG. 4 ; [0036] FIG. 9A is a waveform chart illustrating a power supply voltage input terminal VDD of a CMOS inverter shown in FIG. 8 ; [0037] FIG. 9B is a waveform chart illustrating a gate input terminal C of a CMOS inverter shown in FIG. 8 ; and [0038] FIG. 9C is a waveform chart illustrating an output voltage terminal Vout of a CMOS inverter shown in FIG. 8 . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0039] In the following, embodiments of the present invention will be described with reference to the accompanying drawings. [0040] FIG. 4 is a circuit diagram showing an embodiment of a reset device to which the present invention is applied. In FIG. 4 , the reset device according to the present embodiment includes a power supply voltage input terminal VDD and a ground input terminal GND. A power supply voltage is input between the power supply voltage input terminal VDD and the ground input terminal GND and a reset signal is output from an output terminal Vout. The reset device according to the present embodiment may be applied to a reset IC (integrated circuit), for example. Thus, the reset signal output terminal Vout may be connected to a reset signal input terminal of a CPU (not shown in the drawings) and the reset device may be used as a reset IC for CPU. [0041] In FIG. 4 , the reset device according to the present embodiment is substantially separated into a power supply voltage monitoring unit 10 and a reset signal outputting unit 20 . The power supply voltage monitoring unit 10 detects a detection voltage based on a power supply voltage supplied between the power supply voltage input terminal VDD and the ground input terminal GND and monitors the magnitude of the power supply voltage. In addition, the power supply voltage monitoring unit 10 compares the detected voltage with a reference voltage and outputs a comparison result. The reset signal outputting unit 20 outputs a reset signal or a reset release signal based on the comparison result output from the power supply voltage monitoring unit 10 . [0042] The power supply voltage monitoring unit 10 includes resistors R 1 , R 2 , and R 3 , a constant-current source 11 , a Zener diode 12 , a comparator 13 , and an N-channel MOS (Metal Oxide Semiconductor) transistor 14 . The MOS transistor applied to the reset device according to the present embodiment may employ a MOSFET (MOS field-effect transistor). [0043] The resistors R 1 , R 2 , and R 3 constitute a voltage divider circuit and divide voltage input between the power supply voltage input terminal VDD and the ground input terminal GND in accordance with a resistance ratio so as to detect a detection voltage for comparing with a reference voltage. The detection voltage detected at an A point between the resistor R 1 and the resistor R 2 is input to an inverting input terminal 15 of the comparator 13 . [0044] The constant-current source 11 generates a constant current in accordance with an input voltage. The current generated by the constant-current source 11 is supplied to the Zener diode 12 . [0045] The Zener diode 12 generates a voltage in accordance with the current supplied from the constant-current source 11 . The voltage generated by the Zener diode 12 is used as the reference voltage and input to a noninverting input terminal 16 of the comparator 13 . In other words, the constant-current source 11 and the Zener diode 12 constitute a circuit for generating a reference voltage. [0046] In the comparator 13 , the detection voltage detected at the A point in the voltage divider circuit is input to the inversion input terminal 15 and the voltage generated by the Zener diode 12 in the reference voltage generating circuit is input to the noninversion input terminal 16 so as to compare the detection voltage with the reference voltage. If the detection voltage at the point A is assumed to be VA and the reference voltage is assumed to be VREF, the comparator 13 outputs an inversion signal when the detection voltage VA is higher than the reference voltage VREF. By contrast, when the reference voltage VREF is higher than the detection voltage VA, the comparator 13 outputs a noninversion signal. Accordingly, when the detection voltage VA is higher than the reference voltage VREF, the comparator 13 outputs an L-level signal and when the reference voltage VREF higher than the detection voltage VA, the comparator 13 outputs an H-level signal. [0047] In the N-channel MOS transistor 14 , a gate is connected to an output terminal of the comparator 13 , a drain is connected to a B point between the resistor R 2 and the resistor R 3 in the voltage divider circuit, and a source is connected to a ground line 51 from the ground input terminal GND. Thus, if the N-channel MOS transistor 14 is set to output a voltage not less than 0.7V and conducts when the output from the comparator 13 is at the H level, an electric potential at the point B becomes 0V. [0048] In accordance with this configuration, a threshold voltage of the detection voltage VA based on the power supply voltage for outputting a reset signal is expressed by VA=VDD*(R 2 +R 3 )/(R 1 +R 2 +R 3 ) when the detection voltage VA is higher than the reference voltage VREF or by VA=VDD*R 1 /(R 1 +R 2 ) when the detection voltage VA is lower than the reference voltage VREF, so that it is possible to set the threshold voltage to have hysteresis. [0049] In the present embodiment, the hysteresis voltage is set for the threshold of the detection voltage based on the power supply voltage for generating the reset signal. However, the detection voltage may be compared with the reference voltage based on the same voltage dividing without setting the hysteresis voltage in particular. In the power supply voltage monitoring unit 10 , it is sufficient to determine whether the power supply voltage exceeds the threshold for generating the reset signal or the reset release signal based on the comparison with the reference voltage, so that various types of forms may be applied to the detection of the power supply voltage and a method for setting the reference voltage. [0050] Next, the reset signal outputting unit 20 is described. The reset signal outputting unit 20 includes three stage CMOS (Complementary MOS) inverters 21 , 22 , and 23 . In FIG. 4 , the reset signal outputting unit 20 is constructed using the three stage CMOS inverters 21 , 22 , and 23 . However, the reset signal outputting unit 20 may be constructed using a single stage CMOS inverter or may be constructed using five stage CMOS inverters, for example. Further, it is possible to dispose an even number of CMOS inverters as long as matching of inversion and noninversion is obtained. [0051] The CMOS inverters 21 , 22 , and 23 are constructed using combinations of P-channel MOS transistors 31 , 32 , and 33 and N-channel MOS transistors 41 , 42 , and 43 , respectively. The CMOS inverters 21 , 22 , and 23 are configured such that gates of the P-channel MOS transistors 31 , 32 , and 33 and drains of the N-channel MOS transistors 41 , 42 , and 43 are respectively connected and each combination has the same input/output terminal. [0052] On the other hand, sources of the P-channel MOS transistors 31 , 32 , and 33 are connected to a power supply voltage line 50 connected to the power supply voltage input terminal VDD. Further, sources of the N-channel MOS transistors 41 , 42 , and 43 are connected to the ground line 51 connected to the ground input terminal GND. Moreover, a resistor R 4 is disposed as an impedance unit between the N-channel MOS transistor 41 and the ground line 51 and a resistor R 5 is disposed as an impedance unit between the P-channel MOS transistor 32 and the power supply voltage line 50 . [0053] In the CMOS inverters 21 , 22 , and 23 , when an L-level input signal is input to the gate, the P-channel MOS transistors 31 , 32 , and 33 conduct, N-channel MOS transistors 41 , 42 , and 43 do not conduct, and an H-level voltage is output from the drain. By contrast, when an H-level input signal is input to the gate, the P-channel MOS transistors 31 , 32 , and 33 do not conduct, the N-channel MOS transistors 41 , 42 , and 43 conduct, and an L-level output signal is output from the drain. In accordance with this, the CMOS inverters 21 , 22 , and 23 are each configured to output an inversion signal in response to the input signal. In addition, preferably, the P-channel MOS transistors 31 , 32 , and 33 and the N-channel MOS transistors 41 , 42 , and 43 are constructed using FETs of the same type such that each transistor is switched on and off using the same switching voltage. [0054] In the following, each of the CMOS inverters 21 , 22 , and 23 are described. FIGS. 5A , 5 B, 5 C, and 5 D are diagrams illustrating operation of the CMOS inverter 21 . FIG. 5A a circuit diagram showing a configuration of the CMOS inverter 21 of FIG. 4 in an enlarged manner. [0055] In FIG. 5A , as mentioned above, the CMOS inverter 21 is constructed using the P-channel MOS transistor 31 and the N-channel MOS transistor 41 in an integrated manner such that both gates and both drains are connected to constitute the input terminal and the output terminal. Further, the resistor R 4 is disposed as the impedance unit between the source of the N-channel MOS transistor 41 and the ground line 51 . [0056] In FIG. 5A , no impedance unit is disposed between the P-channel MOS transistor 31 and the power supply voltage line 50 while only the resistor R 4 is disposed between the N-channel MOS transistor 41 and the ground line 51 . Accordingly, when impedance between a VIN and the power supply voltage line 50 is compared with impedance between the VIN and the ground line 51 , the impedance between the VIN and the ground line 51 is higher than the impedance between the VIN and the power supply voltage line 50 . Thus, current is more readily flown between the VIN and the power supply voltage line 50 in comparison with the case between the VIN and the ground line 51 . And, the magnitude of the switching voltage for switching on and off the P-channel MOS transistor 31 and the N-channel MOS transistor 41 is increased. [0057] FIGS. 5B , 5 C, and 5 D are 5 B are waveform charts showing a relationship of voltage waveforms among the power supply voltage input terminal VDD, the input terminal VIN, and the output terminal Vout of the CMOS inverter 21 . [0058] In FIG. 5B , the voltage waveform of the power supply voltage input terminal VDD indicates that an input power supply voltage exceeds a threshold of the reset signal and a reset status is released. The following describes a case where a voltage waveform including a rapid voltage change such as a noise is input and voltage becomes high at a certain portion. [0059] In this case, as shown in FIG. 5C , the VIN is influenced by the rapid voltage change of the power supply voltage VDD, so that the voltage of the VIN becomes high at the same time. As described with reference to FIGS. 3A , 3 B, and 3 C, when Vth=VDD/2 remains unchanged, the portion where the rapid voltage change has occurred exceeds the threshold of the switching voltage of the CMOS inverter 21 , so that the L level is temporarily switched to the H level. However, in FIG. 5C , the threshold Vth of the switching voltage is raised, so that the L level is maintained without causing the switching. Thus, the output voltage Vout remains unchanged and it is possible to maintain the output voltage Vout at the H level. [0060] In this manner, by adjusting the impedance between the input terminal VIN of the CMOS inverter 21 and the power supply voltage line 50 using the resistor R 4 , it is possible to adjust the switching voltage for switching on and off in the CMOS inverter 21 and to construct the CMOS inverter 21 as a stable inverter which is not influenced even when the rapid voltage change has occurred in the power supply voltage. [0061] FIGS. 5A , 5 B, 5 C, and 5 D describe the case where the switching voltage is raised. However, by disposing the resistor R 5 as the impedance unit between the P-channel MOS transistor 32 and the power supply voltage line 50 as shown in the CMOS inverter 22 of FIG. 4 , it is possible to lower the switching voltage for switching on and off in the CMOS inverter 22 . Thus, even when the input voltage VIN at the H level is lowered to some extent due to the rapid voltage change, it is possible to maintain the H-level input and to output an output signal at the L level. [0062] Further, in FIG. 4 , the resistor R 4 is disposed between the N-channel MOS transistor 41 and the ground line 51 in the CMOS inverter 21 and the resistor R 5 is disposed between the P-channel MOS transistor 32 and the power supply voltage line 50 in the CMOS inverter 22 , so that the impedance units are disposed continuously on different lines in two stages. In accordance with this, when an input signal to the CMOS inverter 21 is at the H level, an L-level output signal is output as inversion. Then, the L-level signal is input to the following CMOS inverter 22 as an input signal and an H-level signal is output as inversion. Thus, a multistage structure is formed in which both inverters are stable upon voltage change in the same direction (increase direction) relative to the input of the power supply voltage. In this manner, not only by raising the switching voltage in the CMOS inverter 21 , but also by lowering the switching voltage in the following CMOS inverter 22 , it is possible to deal with the rapid change of the power supply voltage separately in two stages. [0063] In FIG. 4 , the CMOS inverter 23 at a third stage includes no resistor. As in this case, it is not necessary to dispose resistors on all of the CMOS inverters 21 , 22 , and 23 and the switching voltage may be adjusted by disposing the resistor on the stage requiring the resistor. By contrast, the resistors may be disposed on all of the CMOS inverters 21 , 22 , and 23 . [0064] The following describes a relationship between magnitude of resistance in the CMOS inverters 21 and 22 applied to the reset device according to the present embodiment and the switching voltage. [0065] FIG. 6 is a diagram showing a relationship between a resistance value and the switching voltage when the resistor R 5 is inserted between the source of the P-channel MOS transistor 32 and the power supply voltage line 50 as in the CMOS inverter 22 shown in FIG. 4 . In FIG. 6 , a horizontal axis indicates a resistance value (kΩ) and a vertical axis indicates the switching voltage (V). [0066] In FIG. 6 , when the resistance value is less than 100 kΩ, a change of the switching voltage in accordance with a change of the resistance value is large. When the resistance value is not less than 100 kΩ, the change of the switching voltage is reduced and becomes stable. When the switching voltage is greatly changed relative to the change of the resistance value in an excessive manner, an influence of the resistor R 5 becomes too large, so that the resistor R 5 becomes less applicable to an actual circuit. In accordance with this, in FIG. 6 , preferably, a resistance value in a relatively stable range not less than 100 kΩ is applied to the resistor R 5 . For example, preferably, the resistance value of the resistor R 5 inserted between the source of the P-channel MOS transistor 32 and the power supply voltage line 50 is within a range from not less than 100 kΩ to not more than 3 MΩ and more preferably within a range from not less than 150 kΩ to not more than 2 MΩ. It is even more preferable to have a range from not less than 200 kΩ to not more than 1 MΩ and the range is optimized at about 300 kΩ, namely, from not less than 250 kΩ to not more than 350 kΩ. [0067] FIG. 7 is a diagram showing a relationship between the resistance value and the switching voltage when the resistor R 4 is inserted between the source of the N-channel MOS transistor 41 and the power supply voltage line 50 as in the CMOS inverter 21 shown in FIG. 4 , for example. In the same manner as in FIG. 6 , a horizontal axis indicates the resistance value (kΩ) and a vertical axis indicates the switching voltage (V). [0068] FIG. 6 and FIG. 7 are different in that FIG. 6 describes decreasing characteristics in the right direction and FIG. 7 describes increasing characteristics in the right direction. However, FIG. 6 and FIG. 7 are the same in that the change of the switching voltage relative to the change of the resistance value is large when the resistance value is less than 100 kΩ and the change of the switching voltage relative to the change of the resistance value is small when the resistance value is not less than 100 kΩ. In this case, when the switching voltage is greatly changed relative to the change of the resistance value in an excessive manner, the resistor R 4 becomes less applicable to an actual circuit. In accordance with this, preferably, the resistance value of the resistor R 4 is not less than 100 kΩ. Thus, for example, preferably, the resistance value of the resistor R 4 inserted between the source of the N-channel MOS transistor 41 and the ground line 51 is within a range from not less than 100 kΩ to not more than 3 MΩ and more preferably within a range from not less than 150 kΩ to not more than 2 MΩ. It is even more preferable to have a range from not less than 200 kΩ to not more than 1 MΩ and the range is optimized at about 300 kΩ, namely, from not less than 250 kΩ to not more than 350 kΩ. [0069] In this manner, the resistance values of the resistor R 4 and the resistor R 5 in the CMOS inverter 21 and the CMOS inverter 22 applied to the reset device according to the present embodiment are preferably within a range from several 100 kΩ to several MΩ. [0070] FIG. 8 is a circuit diagram showing a configuration of a CMOS inverter 24 as a variation in the reset device shown in FIG. 4 . [0071] In FIG. 8 , the CMOS inverter 24 is different from the inverter shown in FIG. 4 and FIG. 5A in that the CMOS inverter 24 includes a CR time constant circuit constructed using a resistor R 6 and a capacitor C 1 . Further, the CMOS inverter 24 in FIG. 8 is different from the inverter in FIG. 4 and FIG. 5A in that a resistor R 7 is disposed between a P-channel MOS transistor 34 and the power supply voltage line 50 and a resistor RB is disposed between an N-channel MOS transistor 44 and the ground line 51 . [0072] In FIG. 8 , by inserting the CR time constant circuit before an input of the CMOS inverter 24 , even when the VDD with a square wave is input, a voltage to be input to an input terminal of the CMOS inverter 24 is input with a voltage waveform having rising of time delay. [0073] In the following, operation of the CMOS inverter 24 in FIG. 8 is described with reference to FIGS. 9A , 9 B, and 9 C. FIGS. 9A , 9 B, and 9 C are waveform charts illustrating voltage waveforms of a power supply voltage input terminal VDD, a gate input terminal C, and an output voltage Vout. In each waveform chart, a horizontal axis indicates time and a vertical axis indicates magnitude of voltage. FIG. 9A shows a change of the voltage waveform relative to a temporal change of the power supply voltage input terminal VDD. FIG. 9B shows a change of the voltage waveform relative to a temporal change of the gate input terminal C. FIG. 9C shows a change of the voltage waveform relative to a temporal change of the output voltage Vout. [0074] As shown FIG. 9A , when a voltage is input to the power supply voltage input terminal VDD at t=t 0 , an input voltage to the gate input terminal C in the CMOS inverter 24 is gradually rising as shown in FIG. 9B . In this case, when the switching voltage in the CMOS inverter 24 is set as V 1 , a switching time is set as t=t 1 . Accordingly, an output time becomes t=t 1 as shown in FIG. 9C . [0075] On the other hand, when the switching voltage is set as V 2 , the switching time is set as t=t 2 , as shown in FIG. 9B . Accordingly, Vout is output at t=t 2 as shown in FIG. 9C . [0076] In this manner, in the CMOS inverter 24 including the CR time constant circuit, by adjusting and setting the switching voltage relative to the input voltage, it is possible to adjust the output time of the output signal Vout. [0077] With reference to FIG. 8 , the configuration and a relationship are described. In FIG. 8 , the switching voltage in the CMOS inverter 24 is set using both resistor R 7 disposed between the P-channel MOS transistor 34 and the power supply voltage line 50 and resistor RB disposed between the N-channel MOS transistor 44 and the ground line 51 . In the configuration shown in FIG. 4 and FIG. 5A , it is sufficient to merely raise or lower the switching voltage, so that the resistor is inserted between one of the MOS transistors and the line. However, in order to adjust the output time, it is necessary to set a ratio of the increase or decrease of the switching voltage in a more accurate manner, so that the adjustment is readily and accurately made by using a resistance ratio on both sides in a quantitative manner. In the same manner as in FIG. 1 and FIGS. 5A , 5 B, 5 C, and 5 D, when a value of the resistor R 7 is raised, the switching voltage is lowered and when a value of the resistor RB is raised, the switching voltage is lowered. [0078] When the CR time constant circuit is applied as in the CMOS inverter 24 according to the present embodiment, it is possible to adjust the switching voltage of the output voltage signal Vout by adjusting the relationship between the CR time constant and the CMOS inverter 24 . [0079] The present invention is not limited to the specifically disclosed embodiment, and variations and modifications may be made without departing from the scope of the present invention. [0080] The present application is based on Japanese priority application No. 2006-299315 filed Nov. 2, 2006, the entire contents of which are hereby incorporated herein by reference.

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